San Diego State University

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The multiple GHz clock speeds of a microprocessor'’s internal logic typically cannot be maintained for its off-chip signals. The main bottleneck causing this IC vs. packaging performance gap is the electrical properties of interconnects and packages. They behave as distributed circuits, causing reflections, attenuation, dispersion, and crosstalk. Moreover, high-speed digital signals are affected by power supply noise, and cause increased electromagnetic interference due to discontinuities in the transmission-line reference planes.

Dr. Engin's research is in the area of electromagnetic interference with focus on signal/power integrity modeling and numerical electromagnetics applied to microelectronic packages and 3D stacked ICs. He has been researching new modeling and analysis methodologies for electrical design of interconnects, packages, and power delivery networks and has developed novel algorithms and design tools for advanced packaging that enables high-speed and high-performance systems.

Grants

• 01/2025-03/2025 Hitachi Japan, Electrical Modeling of 2.xD / 3D Package for Chiplets, PI, $10K.
• 11/2024-10/2025 NSF, Collaborative Research: S-STEM: Planning for CYBER: Community Bridge to Engineering and Research, PI, $100K.
• 09/2014-08/2019 NSF, Determination of High-Frequency Properties of Integrated Circuit Packages, PI, $291K.
• 11/2016-09/2017 Sumitomo Corp. Japan, Stepped Impedance Common-Mode Filter in Differential Lines, PI, $25K.
• 12/2015, Alexander-von-Humboldt Research Fellowship, PI, $69K
• 8/2015, Gift from Oak Mitsui Corporation, PI, $10K
• 10/2011-3/2013 NEC Corporation, Japan, Efficient Simulation Methodology for Complex Power Delivery Networks, PI, $80K.
• 2011-2013 Summer Visiting Faculty at U.S. Air Force Rome Research Laboratory/Information Institute, Electrical Model Extraction for Interconnects in 3D ICs, PI, $71K.
• 01/2014 Gift from Kyocera America, PI, $1K.
• 06/2013 Gift from Oak Mitsui Corporation, PI, $5K.
• 3/2013-3/2014 California Energy Commission, Electroporation of Algal Biomass to Enhance Methane Gas Production, (Co-PI).
• 06/2017-08/2017 SDSU Summer Undergraduate Research Program: High-Frequency Characterization of Flip-Chip Packages, PI, $3K.
• 01/2014-06/2015 SDSU University Grants Program, High-Frequency Chip Package Characterization, PI, $9K.
• 01/2012-06/2013 SDSU University Grants Program, Electrical Design, Modeling and Simulation of 3D Integrated Circuits, PI, $10K.
• 01/2010-06/2011 SDSU University Grants Program, Analysis and Characterization of Ultra-High-Speed Interconnects, PI, $10K.
• 2005-2007 At Georgia Institute of Technology in Research Contract from Panasonic, Panswitch-Customized Simultaneous Switching Noise Simulator, $250K (Co-PI).

Awards

• 2017 IEEE EMC-S M.Kanda Award for the most cited paper in the last 5 years (2013-2017)
• 2015 Outstanding Educator Award from the International Microelectronics Packaging and Assembly Society
• 2015-2018 Alexander-von-Humboldt Research Fellow
• 2009 Semiconductor Research Corporation Inventor Recognition Award
• Best paper awards at IMAPS, IEEE ECTC, DesignCon
• 2005 Packaging Research Center (PRC) Award for the fastest start and program management in PRC, Georgia Institute of Technology, Atlanta, GA
• 2004 Summa Cum Laude from the University of Hannover, Germany
• 2001 Dean's Award from the University of Paderborn, Germany

Patents

• A. E. Engin, G. Aguirre, K.-D. Lang, and I. Ndip, Non-overlapping power/ground planes for localized power distribution network design - United States Patent: 11,330,699. Applications also filed in Germany, China, and Japan, May 2022.
• T. H. Kim, A. E. Engin, and M. Swaminathan, Systems and methods for electromagnetic band gap structure synthesis - United States Patent: 8,060,457, Nov. 2011.
• A. E. Engin and M. Swaminathan, Multilayer finite difference methods for electrical modeling of packages and printed circuit boards - United States Patent: 7,895,540, Feb. 2011.
• M. Swaminathan, A. E. Engin, P. Muthana, and L. Wan, Packaging having an array of embedded capacitors for power delivery and decoupling in the mid-frequency range and methods of forming thereof - United States Patent: 7,504,706, Mar. 2009.
• M. Swaminathan, A. E. Engin, P. Muthana, and K. Srinivasan, Device having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry of an integrated circuit - United States Patent: 7,705,423, Apr. 2010.